Magnetoresistive random access memory (MRAM) is a memory technology that may replace dynamic random access memory (DRAM) as the standard memory for computing devices. Non-volatile MRAMs allow for “instant on” systems, i.e., systems that come to life as soon as the computer system is turned on.
An MRAM cell includes a structure having ferromagnetic layers separated by a non-magnetic tunneling barrier layer that are arranged into a magnetic tunneling junction (MTJ). Digital information is stored and represented as specific orientations of magnetic moment vectors in the ferromagnetic layers. More particularly, the magnetization of one ferromagnetic layer (reference layer) is magnetically fixed or pinned, while the magnetization of the other ferromagnetic layer (free layer) can be switched between two preferred directions in the magnetization easy axis. The magnetization easy axis is typically selected to be in parallel alignment with the fixed magnetization of the ferromagnetic reference layer. Relative orientations of the free layer magnetization are also known as “parallel” and “antiparallel” states, respectively, which exhibit two different resistance values in response to a voltage applied across the magnetic tunneling junction (MTJ) barrier layer. Hence, the resistance of the MTJ reflects a specific state, which is decreased when the magnetization is parallel and increased when the magnetization is antiparallel. Detection of resistivity allows an MRAM cell to provide logic information assigned the two different resistivity states.
An MRAM cell is written by the application of magnetic fields that are made to be coupled to the free layer magnetization and generated by bi- or uni-directional currents running through current lines positioned adjacent to the memory cell.
Fabrication of MRAM cells is typically integrated into the back end wiring structure in conventional back-end-of-line CMOS processing.
To be useful in present day electronic devices, particularly, in portable apparatuses such as notebook computers, digital still cameras, and the like, very high-density arrays of magnetic memory cells are required. Accordingly, scaling down the memory cell size is an essential precondition for practical usage. However, there are many obstacles to successfully down-sizing MRAM cells. One problem that arises in scaling-down MRAM cells is that the magnetic switching fields for reversing the ferromagnetic free layer magnetization increase at approximately 1/√{square root over (w)}, where w is the width of the cell. Thus, if MRAM cells become smaller and smaller, field selected switching becomes more difficult. Hence, strong magnetic fields are required for field selected switching, i.e., large switching currents running through the current lines.
In order to overcome the problem of increased switching currents, a ferromagnetic liner has been added around the current lines to lower the power consumption due to a concentration or focusing of the magnetic flux, and requiring smaller switching currents. Also, the ferromagnetic liners act as genetic shields to prevent adjacent memory cells from being inadvertently switched. In general, such ferromagnetic liners are fabricated using two different strategies.
In a first approach, using a conventional damascene process, a trench is formed in an insulating material above a magnetic tunnel junction (MTJ), followed by creating ferromagnetic side wall spacers in the trench and filling the trench with a conductive material, such as Copper (Cu), that is polished to remove conductive material outside the trench to produce a conductive line in the trench. After polishing, a ferromagnetic cap layer is deposited on top of the line, for example, using an electro(less) plating technique. Such a manufacturing process involves many process steps and, therefore, is both cost and time consuming. Otherwise, process conditions of electro(less) plating are critical regarding purity of the deposited layer, which is very likely to result in severe quality problems (formation of seeds between the lines). Furthermore, polishing the conductive material followed by deposition of a cap layer results in an approximately 90° corner of ferromagnetic layers (side walls and cap layer), which, however, should be avoided in view of a magnetic flux leakage likely to occur at the corners. Moreover, if the ferromagnetic cap layer is deposited by sputtering and followed by a patterning via lithography and metal etching, the overlay errors can be critical with respect to the magnetic flux closure between the sidewall spacers and the cap layer.
In a second approach to create a ferromagnetic liner, in a sacrificial insulating material process, an up-standing metal line that projects from the insulating material is created most practically using electro-chemical growth, i.e., an electro(less) plating technique, followed by depositing a ferromagnetic liner using also a surface-selective electro(less) plating technique. As described above in connection with the damascene process, the plating process is the critical process with respect quality problems in view of a lacking purity of the deposited layer. After an up-standing metal line that projects from the insulating material is created, the ferromagnetic liner may also be deposited using a sputtering process at least over the metal line that then is patterned via lithography and metal etching. As described in connection with the damascene process, this requires an additional lithography step and the overlay errors can be critical with respect to the magnetic flux concentration effect.
An improved method of fabricating a magnetoresistive memory cell that allows for improved fabrication of a ferromagnetic liner is desirable.